The present invention relates generally to design and manufacture of integrated circuits, and more particularly, to systems, methods and apparatus for routing wires on a layer in an integrated circuit.
Integrated circuit designs often include more than one routing wire pitch including different wire widths and/or different spacing between the wires of same or different widths. The different routing wire pitches are often used to satisfy the often conflicting goals of current load, timing (i.e., data transmission speed) and area of the die consumed. A wider wire pitch including either wider spaces between the wires and/or wider wire width, typically provides faster transmission speed. Therefore a wider wire pitch is typically used for timing critical signal paths to satisfy timing goals.
A narrower wire pitch includes either closer spaced wires and/or narrower wire width. Narrower wire pitches typically provide a slower transmission speed and is therefore used for signal paths that are not timing critical. Narrower wire pitches are typically compressed as close as design constraints allow to reduce the overall die size of the resulting integrated circuit.
The wires are routed across the semiconductor die in specified routes commonly referred to as a routing channel. Unfortunately, the typical approach to combining wider pitch wires and narrower pitch wires in a common routing channel typically results in an inefficient use of the available space in the routing channel and can result in increasing the overall size of the die.
In view of the foregoing, there is a need for more efficiently routing wires having more than one pitch in a common routing channel